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XMEGA A [MANUAL]
8077I–AVR–11/2012
19.3.8 Arbitration
A master can start a bus transaction only if it has detected that the bus is idle. As the TWI bus is a multi-master bus, it is
possible that two devices may initiate a transaction at the same time. This results in multiple masters owning the bus
simultaneously. This is solved using an arbitration scheme where the master loses control of the bus if it is not able to
transmit a high level on the SDA line. The masters who lose arbitration must then wait until the bus becomes idle (i.e.,
wait for a STOP condition) before attempting to reacquire bus ownership. Slave devices are not involved in the arbitration
procedure.
Figure 19-9. TWI arbitration.
Figure 19-9 shows an example where two TWI masters are contending for bus ownership. Both devices are able to issue
a START condition, but DEVICE1 loses arbitration when attempting to transmit a high level (bit 5) while DEVICE2 is
transmitting a low level.
Arbitration between a repeated START condition and a data bit, a STOP condition and a data bit, or a repeated START
condition and a STOP condition are not allowed and will require special handling by software.
19.3.9 Synchronization
A clock synchronization algorithm is necessary for solving situations where more than one master is trying to control the
SCL line at the same time. The algorithm is based on the same principles used for the clock stretching previously
described. Figure 19-10 shows an example where two masters are competing for control over the bus clock. The SCL
line is the wired-AND result of the two masters clock outputs.
Figure 19-10.Clock synchronization.
DEVICE1_SDA
SDA
(wired-AND)
DEVICE2_SDA
SCL
S
bit 7
bit 6
bit 5
bit 4
DEVICE1 Loses arbitration
DEVICE1_SCL
SCL
(wired-AND)
Wait
State
DEVICE2_SCL
High Period
Count
Low Period
Count
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